1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as an electrically rewritable flash memory, and more particularly to a technique for speeding up read operation of the device.
2. Description of the Background Art
A nonvolatile semiconductor memory device such as a flash memory is capable of nonvolatile storage of information by setting each of a plurality of memory transistors forming a memory cell array either to an “H” threshold voltage VthH which is a threshold value higher than read voltage, or to an “L” threshold voltage VthL which is lower than read voltage. The plurality of memory transistors are generally arranged in a matrix such that the drains (drain electrodes) thereof in each column are connected to a bit line, the gates (gate electrodes) thereof in each row are connected to a word line, and the sources (source electrodes) thereof are connected to a common source line.
Speedup is achieved by forming the above bit line used in a nonvolatile semiconductor memory device in a hierarchy that is composed of a main bit line and a sub-bit line. Japanese Patent Application Laid-Open No. 11-191298 (1999) further discloses a nonvolatile semiconductor memory device in which a first transistor for connecting a main bit line and a sub-bit line and a second transistor for discharging the sub-bit line are complimentarily turned on/off.
The nonvolatile semiconductor memory device disclosed in JP 11-191298, however, requires the same number of control signal lines for the first transistor and the second transistor, putting restrictions on wiring in terms of layout. This poses a first problem of an increase in area.
In addition, in JP 11-191298 where the sources of a plurality of memory transistors are connected to a single common source line as discussed above, the common source line is subjected to fluctuations in fixed potential. This poses a second problem of a decline in read operation. This second problem will be described below in detail.
When performing two sequential read operations by selecting a predetermined sub-bit line at the first reading and not selecting it at the second reading, the predetermined sub-bit line is discharged at the second reading when not selected. Thus, it is likely that a certain amount of charge on the predetermined sub-bit line that has been precharged at the first reading remains at the start of the second reading. Particularly when a selected memory transistor has the “H” threshold voltage VthH (which is not turned on with read voltage), the charge on the predetermined sub-bit line that has been generated at the first reading remains reliably without being discharged to the common source line via the selected memory transistor.
The remaining charge affects potential fluctuations of the common source line at the second reading. For example, there always exists a non-selected memory transistor having a gate connected to a selected word line to which a read voltage is supplied at the second reading, and a drain connected to the above predetermined sub-bit line. This non-selected memory transistor enters an on state when having the “L” threshold voltage VthL, so the charge on the above predetermined sub-bit line flows into the common source line via this non-selected memory transistor. This will result in greater fluctuations in fixed potential of the common source line at the second reading than initially predicted. And the amount of current flowing through the main bit line will be limited with the fluctuations in fixed potential of the common source line, resulting in a decline in read operation.